wafer.space Community - Anybody thought of 1-2 mm² slot to be packaged SOIC-8 package?

I was wandering whether it could be possible to fit 10 to 16 dies in a standard slot in order to go for SOIC-8 packaging. I got some idea about a standard pad frame placement for SOIC-8 packaging that could work with 1.5-2 mm² dies, likely with dedicated ESD protections. It could be very handy for people to implement stand-alone analog IC with 8 pins which allow a lot of classic discrete analog functions. SOIC-8 is easy to handle and solder, and there are inexpensive sockets available to test all your parts without soldering. It seems that SOIC-8 packaging is much cheaper than QFN with large pin numbers. If we were able to dice 10 to 16 dies in a one slot, we could reduce cost and increase access for sub 1000$ entry level to get 1000 SOIC-8 parts. I would personally be interested in designing some op amp stuff, but current prices are too large for hobby. It might really interest some universities for educational program, or even some start-ups needed tailor made discrete IC in small quantities, or prototype new discrete IC product. Wafer.space, what is the smallest die size that can be diced? 1 mm²? would you be willing to offer those? If a community grows and organizes to fill slots, and wafer.space provides final standardized dies for SOIC-8, it could be possible to join orders and get that packaged many thousands of SOIC-8 at little cost. It would be much easier if wafer.space developed this capability directly. Would there be some interest for wafer.space to develop this offer? For all: what do you think about that? Would you be interested in? Should the package size be increased to SOIC-16 to fit more stuff? (edited)

Do you have a link for packaging house doing soic cheap ?

• Selected Package: SOIC • Pins: 16pin • Volume: Low The estimate price is: $0.18 Don’t hesitate to contact us if you have any questions.

Got by email by filling form on https://anysilicon.com/package-price-estimator/ Not sure whether it's possible to really get those prices for 10000-20000 parts. ChatGPT believes that the price for low volume is not so inflated, because those packages are very standard, and basically need 2 lines of pads with some pitch. The website does not have 8 pins. (edited)

IC Package Price Estimator - AnySilicon

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@bobo38 - I have not found anyone who is willing to do the low volume that wafer.space has.

2:47 p.m.

@bobo38 - I started trying to figure out how to do IO only one one side of the die and such at https://mithro.github.io/gf180mcu-project-template/

I plan to submit a one side only quarter slot design as a test - @Leo Moser (mole99) did some changes to the template to allow that to work. As you can see, this allows a decent amount of SRAM on a quarter slot (here 9.5kB):

Tim 'mithro' Ansell

@bobo38 - I started trying to figure out how to do IO only one one side of the die and such at https://mithro.github.io/gf180mcu-project-template/

yeah maybe just one edge with IO would allow low pin count small dies. @RebelMike , I would rather remove the corner cells, as they only make sense to connect an adjacent edge I would say

Yeah, that would make sense, I haven’t looked into how this actually works in the pad ring script.

@RebelMike - Oh, super cool!

1:14 a.m.

@bobo38 - Most people complain about not having enough I/O, so I'm excited for people who think they can do something with the much more limited 12 or 20 I/O count. I think of 12 I/O as 2 power, 8 bit bidir bus and 2 control while 20 I/O is 16 bit bidir. Packaging is about 1-2 cents a pin + some fixed cost (around ~10-15 cents), so with something like 12 I/O we might be able to get packaging down to $0.50 each.